A Novel Method for Modeling and Co-Simulation of FPGA Package and Board

Abstract

Field Programmable Gate Array (FPGA) circuits have become an integral part of recent embedded process control designs. However, printed circuit board (PCB) layout design has become increasingly challenging due to the various propagation delays associated with FPGA pin count. To compensate for these delays on the PCB side, high-speed PCB interconnect lines are left unmatched, making sign-off of the board a major challenge in the absence of an FPGA model. Unfortunately, FPGA vendors do not provide the behavior model of FPGA; instead, they give only the pin delay report in a comma-separated file format. This file format is not considered by most simulation tools during analysis and simulation, thus limiting signal data rates to 10 Gbps for board-level simulation. Timing violations arise in simulation results if the duration of these signals differs at the board level at these high data rates, and as a result, the board must be redrawn. This paper presents a novel methodology for creating FPGA models that incorporate package delay in the absence of accurate package models on the board, known as package co-simulation. A close-to-actual parametric spice model of the package is generated, which is tested on a high-speed FPGA board. The simulation results of the proposed package model are compared to the absence of the package model results, indicating that the interconnect delay inside the package is considered during board package co-simulation.This methodology is a significant advancement in the field of FPGA circuit design, as it enables designers to create more accurate models of FPGA circuits and optimize PCB layout design while considering the propagation delays and package interconnect delays. It is expected that this methodology will be a valuable tool for future FPGA circuit designs, enabling designers to achieve a higher level of accuracy and efficiency. © 2024 IEEE.